About the Role

We are looking for a Senior Design Engineer specialising in Network-on-Chip (NoC) to design and optimise high-performance interconnect solutions for SoCs and multi-core processors. This role involves developing scalable, low-latency, and power-efficient NoC architectures while collaborating with architecture, verification, physical design, and software teams.

Key Responsibilities

• Design and optimise scalable, high-performance NoC interconnect solutions for SoCs and multi-core processors.

• Conduct traffic modelling, simulations, and bottleneck analysis to improve throughput and latency.

• Collaborate with verification teams on testbench development, functional validation, and debugging.

• Optimise NoC designs for power, performance, and area (PPA) in collaboration with physical design teams.

• Develop customised NoC configurations and integrate third-party IPs to meet application requirements.

• Develop scripts, automation flows, and performance monitoring tools to improve design methodologies.

• Work with chip architects, backend engineers, and software teams to define requirements and optimise interconnect performance for real-world workloads.

Key Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.

• Experience in NoC RTL design; candidates with strong RTL design experience and knowledge of interconnect architectures are also encouraged to apply.

• Strong proficiency in Verilog/SystemVerilog RTL design and synthesis-friendly coding practices.

• Hands-on experience with NoC topologies, such as mesh, ring, torus, and crossbar, and flow control techniques.

• Experience in performance modelling, simulation, and debugging.

• Familiarity with industry-standard EDA tools for synthesis, static timing analysis (STA), and power analysis.

• Strong understanding of on-chip communication protocols, such as AXI, CHI, PCIe, and CXL.

• Good problem-solving skills and ability to work in a fast-paced, collaborative environment.

Preferred Qualifications

• Experience with NoC-specific tools such as Arteris, NetSpeed, or OpenSoC.

• Familiarity with cache coherence protocols, including MESI/MOESI and CCIX.

• Knowledge of hardware security, fault tolerance, and reliability in NoC design.

• Scripting skills in Python, Perl, or Tcl for automation and debugging.

• Experience with chiplet interconnects and heterogeneous computing architectures.