Job ID:
43150
Published date:
21-07-2026
Summary
Our client is in semiconductor industry. Currently they are looking for Physical Design Engineer to join their team.
Key Responsibilities
- Perform backend IC physical design implementation (PnR) from Synthesis to GDSII.
- Execute floorplanning, CTS, STA, signal integrity, EM/IR analysis, ECO, formality, and physical verification.
- Collaborate with IC design, IP, DFT, and EDA teams to deliver high-quality designs.
- Support timing closure, power optimization, and design sign-off activities.
Requirements
- Bachelor's or Master's Degree in Electrical Engineering, Computer Engineering, or related field.
- Minimum 3 years of semiconductor physical design experience.
- Hands-on experience with Cadence and/or Synopsys physical design tools.
- Strong knowledge of SoC/ASIC implementation flow, STA, CTS, floorplanning, and physical verification.
- Familiar with Linux and scripting (TCL, Shell, Perl, Python, or C++).
- Experience with clocking, clock gating, and power gating methodologies.
- Strong analytical, problem-solving, and communication skills.
For more information or confidential consultation, please do not hesitate to contact Athirah at athirah@bell-ward.com
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Company Registration No.: 1080098-P (JTK License No: JTKSM 427)