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Senior/Staff – Package/Substrate/System Board Design Engineer

Location : Malaysia (Penang, Selangor) and Vietnam (Da Nang, Ho Chi Minh) (on-site) Job Type : Full-time

Malaysians only and/or have permit to work in Malaysia Reporting to : Engineering Lead

Senior/Staff System Board Design Engineer

Key Responsibilities:

• Lead the end-to-end development of complex multilayer system boards, including architecture definition, schematic design & technical decision-making.

• Drive component selection, trade-off analysis & architecture optimization to meet electrical, thermal, and mechanical constraints.

• Ensure high-speed signal integrity, power integrity & EMI/EMC compliance through simulation, design & testing.

• Lead board bring-up, root cause analysis, and system-level debug using lab instruments (oscilloscopes, logic analyzers, spectrum analyzers, etc.).

• Define test strategies and validate hardware against functional, environmental, and reliability requirements.

• Prepare and review detailed design documentation: schematics, BOMs, layout constraints, test reports, and manufacturing files.

• Collaborate with PCB layout engineers on components placements, routing and PCB stack up.

• Skilful on handing rework tool to preforming board rework and modifications to hardware components.

• Collaborate with cross-functional teams including SoC, firmware, packaging, mechanical, and manufacturing teams.

• Interface with suppliers, PCB fabrication and assembly vendors for prototyping and production.

• Provide technical leadership, mentoring, and code/design reviews for junior team members

Requirements:

• Bachelor's or Master’s degree in Electrical or Electronics Engineering. • 8+ years of hands-on experience in high-complexity PCB/system board design. • Proficiency in schematic capture and layout tools (e.g., Cadence Allegro, Altium, OrCAD). • Deep expertise in high-speed digital design (DDR, PCIe, USB, Ethernet, etc.). • Strong understanding of signal and power integrity, simulation techniques, and SI/PI tools (e.g.,

HyperLynx, Sigrity). • Demonstrated experience with board bring-up, lab validation, and production ramp. • In-depth knowledge of DFM/DFT, EMC/EMI, and regulatory compliance requirements. • Excellent problem-solving and analytical skills in solving complex system issues independently. • Highly self-motivated, meticulous, independent with strong ownership on critical deliverables. • Strong interpersonal skills and collaborative across teams. • Preferred Qualifications:

o Experience with designs involving FPGAs, SoCs, PMICs, custom ASICs, or AI/ML accelerators.

o Familiarity with thermal design, power supply design, and mechanical constraints. o Experience in industrial, networking, datacenter, automotive, or medical hardware

development environments. o Knowledge of embedded firmware or system software. o Prior experience with project or technical leadership roles.

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Senior/Staff Package or Substrate Design Engineer Key Responsibilities:

• Designing and developing advanced IC packages and substrates, including 2.5D, 3D, and fan out wafer-level packaging

• Creating detailed layout designs using CAD tools (e.g., Cadence Allegro Package Designer). • Optimizing package designs for electrical performance, thermal dissipation, and mechanical reliability. • Developing and maintaining design rules and guidelines. • Collaborating with IC designers, SIPI engineers, and project teams. • Communicating design requirements and constraints. • Working with external vendors and suppliers. Requirements:

• Degree/Master/PHD in Electrical/electronic Engineering, Materials Science, or a related field • Minimum 5-10 years of professional working experience in package/substrate • Experience with IC packaging technologies and substrate design. • Proficiency in CAD tools for package design (e.g., Cadence Allegro Package Designer). • Knowledge of signal integrity and power integrity principles. • Understanding of thermal management and mechanical reliability. • Familiarity with advanced packaging technologies (e.g., 2.5D, 3D). • Strong analytical and problem-solving skills. • Excellent communication and teamwork skills. Senior/Staff Power integrity Design Engineer Key Responsibilities:

• PDN Analysis and Simulation. • Performing AC and DC analysis of PDNs using simulation tools • Simulating impedance profiles, voltage drops, and current densities to identify potential issues. • Modelling and simulating decoupling capacitor networks to optimize performance. • Analysing transient behaviour and switching noise. • Creating detailed reports and presentations summarizing simulation and measurement results. • Documenting design guidelines and best practices for power integrity. Requirements:

• Degree/Master/PHD in Electrical and Electronics. • Minimum 5-10 years of professional working experience in power intergrity. • Strong understanding of power electronics, circuit theory, and electromagnetic theory. • Proficiency in using power integrity simulation tools • Experience with Package and/or PCB design and layout principles. • Knowledge and experience in interposer is an added advantage. • Knowledge of decoupling capacitor selection and placement. • Strong analytical and problem-solving skills. • Excellent communication and teamwork skills. • Familiarity with industry standards and regulations related to power integrity. • Understanding of thermal analysis is a plus.

NOC Senior Design Engineer

Location: On Site Job Type: Full Time : Malaysians only and/or have permit to work in Malaysia Industry: Semiconductor, Network-on-Chip (NoC), Chip Design

Role Overview

We are seeking a Senior Design Engineer specializing in Network-on-Chip (NoC) to join our cutting-edge semiconductor team. This role involved architecting, designing, and optimizing NoC interconnect solutions for high-performance chips. You will work closely with architects, verification engineers, and software teams to deliver scalable, efficient, and low-latency interconnect designs.

Key Responsibilities

• NoC Architecture & Design: Develop and optimize high-performance, scalable, and low-latency NoC solutions for SoCs and multi-core processors, components, ensuring performance, area, and power efficiency.

• Performance Analysis: Conduct traffic modeling, simulation, and bottleneck analysis to optimize NoC throughput and latency.

• Verification & Validation: Collaborate with verification teams to develop testbenches, ensure functional correctness, and debug issues.

• Power & Area Optimization: Optimize NoC designs for low-power and area-efficient implementations, working closely with physical design teams.

• Integration & Customization: Work on custom NoC configurations, integrating third- party IPs, and tailoring interconnect solutions for specific applications.

• Tool & Flow Development: Enhance NoC design methodologies by developing scripts, automation flows, and performance monitoring tools.

• Cross-functional Collaboration: Work with chip architects, backend engineers, and software teams to define NoC requirements and optimize for real-world workloads.

Requirements • Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering, or related field. • Have experience in NOC RTL Design or experience in RTL Design, bonus if has interconnect architectures • Strong expertise in Verilog/SystemVerilog RTL design and synthesis-friendly coding. • Hands-on experience with NoC topologies (mesh, ring, torus, crossbar, etc.) and flow control

techniques. • Proficiency in performance modeling, simulation, and debugging. • Experience with industry-standard EDA tools for synthesis, static timing analysis (STA), and power analysis. • Strong understanding of on-chip communication protocols (AXI, CHI, PCIe, CXL, etc.). • Excellent problem-solving skills and ability to work in a fast-paced, collaborative environment. Preferred: • Experience with NoC-specific tools (Arteris, NetSpeed, OpenSoC, etc.). • Familiarity with cache coherence protocols (MESI/MOESI, CCIX, etc.). • Knowledge of hardware security, fault tolerance, and reliability in NoC design. • Scripting skills (Python, Perl, Tcl) for automation and debugging. • Experience with chiplet interconnects and heterogeneous computing architectures.

Memory IP Architect / SoC uArchitect Location: Taiwan / Malaysia / Canada / United States / Europe Experience: 15+ Years Report to: CTO

About the Role

We are looking for an experienced Memory IP Architect / uArchitect to lead the architecture and development of next-generation memory solutions for AI, HPC, networking, and custom ASIC applications.

This role will drive the definition of memory subsystems, memory controllers, and high-performance SoC memory solutions from concept through silicon.

Responsibilities

• Define architecture and specifications for Memory IP and SoC subsystems. • Lead memory architecture for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache

subsystems. • Drive architecture trade-offs across performance, power, area, and cost. • Develop performance models and conduct architecture exploration. • Define memory hierarchy, and system-level optimization strategies. • Collaborate with RTL, DV, DFT, PD, Packaging, Firmware, and Software teams. • Support customer engagements, technical reviews, and roadmap planning. • Guide implementation through silicon bring-up and performance tuning.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 15+ years of semiconductor industry experience. • Proven track record delivering complex SoCs or Memory IP from architecture definition to

silicon. • Strong expertise in several of the following:

o DDR5 / LPDDR5X / LPDDR6 o HBM3E / HBM4 o SRAM and Cache Architecture o Memory Controllers and PHY o Memory Coherency o AI Accelerator or HPC Architecture

• Experience with architectural modeling using C/C++, SystemC, or Python.

1) Circuit Design Engineers (Senior-Analogue)

Job Description • Design and implement high speed interfaces and complex mixed-signal circuits using

cutting-edge CMOS tech and EDA tools. • Develop precision analogue blocks related subblocks. • Design blocks such as low offset voltage regulator, bandgap, power detection circuit,

analogue test circuitry, ADC/DAC, Oscillators, power management components. • Work closely with mask designers to deliver the physical design and assist with silicon

evaluation. • Perform architecture studies, circuit designs & simulations, floor-planning, instructing

mask designers, reliability verifications and silicon bring-up.

Qualifications • Degree/Master/PHD in Electrical and Electronics.

• Minimum 5-10 years of professional working experience in analogue circuit design.

• Proficient in circuit design using FinFet tech and EDA tools.

• Experienced in PLL, DLL, Receiver, Transmitter, Voltage regulators, Bandgap, Oscillators, Comparator and others.

• Worked in serial and or parallel interfaces.

• Have understanding in transistor operations.

• Able to work closely with Mask/Layout designers to enable physical design.

• Skilled in teamwork and mentorship.

• Architecture understanding to translate architecture documents to block specifications.

1) Circuit Design Engineers (Senior-Clocking)

Job Description • Design and implement high speed interfaces and complex mixed-signal circuits using

cutting-edge CMOS tech and EDA tools. • Develop clocking circuit like PLL (LC , RO , Fractional ), DLL ,FLL, Delay lines ,

Measurement and ruler circuitry , phase interpolators , DCC, clock tree and clock management units

• Work on serial and parallel interfaces. • Work closely with mask designers to deliver the physical design and assist with silicon

evaluation. • Perform architecture studies, circuit designs & simulations, floor-planning, instructing

mask designers, reliability verifications and silicon bring-up.

Qualifications • Degree/Master/PHD in Electrical and Electronics.

• Minimum 5-10 years of professional working experience in clocking circuit design.

• Proficient in circuit design using FinFet tech and EDA tools.

• Experienced in PLL, DLL, and clocking circuitary as listed in the job description

• Worked in serial and or parallel interfaces.

• Have understanding in transistor operations.

• Able to work closely with Mask/Layout designers to enable physical design.

• Skilled in teamwork and mentorship.

• Architecture involvement for senior role.