Job Responsibilities

• Lead the physical implementation of SoC modules, including ARM CPU and CMN interconnect blocks, covering floorplanning, placement and routing, clock tree synthesis (CTS), timing closure, and physical verification.
• Execute low-power design methodologies and drive optimization of power, performance, and area (PPA).
• Develop, maintain, and enhance backend implementation flows, methodologies, and supporting technical documentation.
• Collaborate closely with front-end design and DFT teams to implement ECOs and resolve timing, logic, and design-related issues.
• Support tape-out activities and contribute to post-silicon yield improvement initiatives.
• Liaise with external design service partners to manage technical interfaces, ensure compliance with delivery requirements, and track issue resolution.

Job Requirements

• Bachelor's degree or higher in Microelectronics, Electrical/Electronic Engineering, or a related field, with at least 3 years of SoC physical design/backend implementation experience.
• Hands-on experience with industry-standard P&R tools such as Innovus and ICC2, along with familiarity in PrimeTime STA, Calibre or ICV for physical verification, and basic knowledge of Design Compiler (DC).
• Strong understanding of low-power design methodologies, timing analysis, and technical problem-solving in backend design.
• Proficiency in Tcl and Python scripting; experience developing automation flows is highly desirable. Familiarity with AI-assisted backend development tools is an added advantage.
• Strong communication, teamwork, and learning capabilities. Experience with 7nm or more advanced technology-node tape-outs is preferred, while TSMC N5A project exposure is highly advantageous.
• Experience collaborating with external design service providers, including alignment of technical interfaces, delivery expectations, and issue management processes.