Responsibilities

• Take ownership of DFT implementation and verification for SoC designs, including Scan insertion, MBIST, and ATPG activities.
• Perform DFT synthesis, timing analysis, and formal verification, while partnering with backend engineers to achieve DFT timing closure.
• Develop test patterns and collaborate with ATE engineers on test program development, validation, and debug activities.
• Analyze production test yield data, identify root causes of test failures, and drive corrective and preventive actions.
• Create and maintain DFT-related design documentation, guidelines, and user manuals.
• Work closely with external design service providers to ensure successful DFT deliverables and timely resolution of technical issues.

Requirements

• Bachelor's degree or higher in Microelectronics, Electrical/Electronic Engineering, or a related discipline, with a minimum of 2 years of hands-on DFT experience.
• Familiarity with industry-standard DFT tools such as Tessent and TestMAX, with a strong understanding of Scan, MBIST, ATPG methodologies, and DFT implementation flows.
• Basic understanding of synthesis and STA concepts, with the ability to support DFT timing constraints and collaborate on timing closure activities with backend design teams.
• Proficient in Tcl and Python scripting, with practical debugging and data analysis capabilities. Experience leveraging AI-assisted tools for DFT development is an added advantage.
• Experience in automotive semiconductor DFT projects is preferred, with working knowledge of ISO 26262 functional safety considerations related to DFT implementation.
• Exposure to ATE debugging, silicon bring-up, or DFT deployment on advanced process nodes will be considered an advantage.
• Proven experience working with external design service providers to manage DFT technical deliverables, interface alignment, and issue resolution.