Job Description

Our client in semiconductor industry is looking for an Analog IC Layout Engineer to support custom analog IP development and full-chip integration.

Key Responsibilities:

• Develop analog layouts including floor planning, device placement, matching, routing, LVS, DRC, DFM, and reliability checks.
• Perform layout optimization, post-layout extraction, and parasitic analysis.
• Collaborate with circuit designers and layout teams on custom IP implementation and tape-out activities.
• Ensure high-quality layout delivery meeting performance, area, and power targets.
• Mentor junior engineers and review layout quality.

Requirements:

• Minimum 3 years of experience in Analog IC Layout.
• Experience with analog layout design, verification, and semiconductor process technologies.

For more information or confidential consultation, please do not hesitate to contact Athirah at athirah@bell-ward.com

We thank you for applying with us in advance but only short-listed candidates will be notified.

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Company Registration No.: 1080098-P (JTK License No: JTKSM 427)