Job Description
Our client is looking for a Digital Verification Engineer to join their growing engineering team. You will be responsible for developing and executing verification environments using UVM methodology to ensure high-quality digital design validation at block and system level. You will work closely with design engineers to define verification strategy, build reusable testbenches, and drive functional and coverage closure.
Key Responsibilities
- Develop UVM-based testbenches for block-level and system-level verification
- Prepare verification plans based on design specifications and functional requirements
- Build reusable verification components including drivers, monitors, scoreboards, and agents
- Implement constrained-random, directed, and coverage-driven test scenarios
- Collaborate with design teams to debug and resolve functional issues
- Support verification closure through coverage analysis and reporting
Requirements
- 3–5 years of experience in digital verification / digital design-related roles
- Bachelor’s degree or above in Electrical Engineering, Computer Engineering, or related field
- Strong proficiency in Verilog / SystemVerilog
- Experience with UVM methodology
- Familiarity with interfaces such as USIT / CHPI / CMPI / iSP
- Experience with display driver IC products or similar semiconductor IP
- Exposure to SoC or IP-level verification environments
For more information or confidential consultation, please do not hesitate to contact Athirah at athirah@bell-ward.com
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Company Registration No.: 1080098-P (JTK License No: JTKSM 427)