Job Description

About the Role

We are looking for an experienced Memory IP Architect / SoC Microarchitect to lead the architecture and development of advanced memory solutions for AI, high-performance computing (HPC), networking, and custom ASIC applications. The role focuses on memory subsystems, memory controllers, and high-performance SoC memory solutions, from architecture definition through silicon implementation.

Key Responsibilities

• Define architecture and specifications for Memory IP and SoC subsystems.

• Lead memory architecture development for DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4, and cache subsystems.

• Evaluate architectural trade-offs involving performance, power, area, and cost.

• Develop performance models and conduct architectural exploration.

• Define memory hierarchy and system-level optimisation strategies.

• Collaborate with RTL, DV, DFT, Physical Design, Packaging, Firmware, and Software teams.

• Support customer engagements, technical reviews, and roadmap planning.

• Guide implementation through silicon bring-up and performance tuning.

Requirements

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

• 15+ years of experience in the semiconductor industry.

• Proven experience delivering complex SoCs or Memory IP from architecture definition through silicon implementation.

• Strong expertise in several of the following areas:

  • DDR5, LPDDR5X/LPDDR6, HBM3E/HBM4

  • SRAM and cache architecture

  • Memory controllers and PHY

  • Memory coherency

  • AI accelerator or HPC architecture

• Experience in architectural modelling using C/C++, SystemC, or Python.