Job Description

Join a highly skilled team focused on advanced semiconductor hardware development. In this role, you will contribute across the full DFT design lifecycle, collaborating with cutting-edge technologies and global industry leaders.

Key Responsibilities

• Implement DFT features including Scan, MBIST, LBIST, and JTAG
• Integrate and connect IP-level test circuitry
• Perform fault coverage analysis, including calculation, evaluation, and optimization
• Develop and generate test patterns
• Execute comprehensive DFT validation

Requirements

• 3–10 years of experience in DFT design
• Hands-on experience with major EDA tools such as Synopsys, Cadence, or Siemens EDA
• Experience in advanced technology nodes (e.g., 7nm / 5nm / 3nm)
• Prior experience in a team lead or sub-lead role
• Strong multicultural communication skills

For more information or confidential consultation, please do not hesitate to contact Athirah at athirah@bell-ward.com

We thank you for applying with us in advance but only short-listed candidates will be notified.

For candidates who applied to this job is deemed to have consented to the collection, use and disclosure of personal data by our organization for a purpose of this or any job application with Bell Ward.

Company Registration No.: 1080098-P (JTK License No: JTKSM 427)