Job Description

We are partnering with a leading player in the semiconductor industry where they are looking for a Physical Design Engineer. This role offers the opportunity to work on advanced hardware development projects with exposure to global collaborations and cutting-edge technologies.

Key Responsibilities:

• Execute digital LSI physical design activities throughout the implementation cycle, from synthesis to physical sign-off.
• Develop and optimize logic synthesis to achieve design, timing, and power targets.
• Perform place-and-route (P&R), including floorplanning, clock tree synthesis (CTS), routing, and physical optimization.
• Conduct static timing analysis (STA) and timing closure to ensure performance requirements are met.
• Carry out power integrity and power-related verification to improve design reliability.
• Perform physical verification, including DRC/LVS checks and sign-off validation.
• Collaborate with cross-functional engineering teams to resolve implementation challenges and deliver high-quality silicon.
• Contribute to process improvements and technical discussions to enhance design efficiency and project execution.

Requirements:

• Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 3–10 years of hands-on experience in digital LSI/ASIC physical design.
• Practical knowledge of the complete RTL-to-GDSII implementation flow.
• Proficiency with industry-standard EDA tools, such as Synopsys, Cadence, or Siemens EDA solutions.
• Strong understanding of physical implementation, timing optimization, and design verification methodologies.
• Good analytical, troubleshooting, and problem-solving skills.
• Effective communication skills with the ability to collaborate in a team environment.
• Experience implementing designs on advanced technology nodes (7nm, 5nm, 3nm, or below).
• Exposure to high-performance or low-power SoC/ASIC development projects.
• Experience leading project modules, mentoring junior engineers, or serving as a technical lead.

For more information or confidential consultation, please do not hesitate to contact Athirah at athirah@bell-ward.com

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Company Registration No.: 1080098-P (JTK License No: JTKSM 427)